1. Field of the Invention
The present invention relates to techniques to restore a power supply control target unit (power domain) within a semiconductor integrated circuit from a power supply shutoff state.
2. Description of the Related Art
The recent trend toward energy savings for environmental considerations has led to an increased demand for reduced power consumption in semiconductor integrated circuits. For example, to reduce power consumption, a power supply to part of sub-systems (power supply control target unit) in a semiconductor integrated circuit may be temporarily shut off while the functions of the sub-systems are not being used.
When a sub-system to which the power supply has been shut off is to be restored, the sub-system needs to be initialized after the power is supplied thereto and thus is initialized before entering normal operations. Japanese Patent Application Laid-Open No. 2002-312073 discusses a technique to restore a power supply from a state where the power supply is shut off and a reset signal (RS) is active, the supply of power and a clock is started (restarted) simultaneously. Here, a reset time corresponding to an operation clock frequency is set in advance in a counter, and after the power and the clock start being supplied, the set reset time is timed. Then, the reset signal is canceled to return to the normal operation state.
During an initialization operation, a state is initialized by causing a signal change in a storage element such as a flip-flop inside a sub-system, and thus the circuit needs to be operated in a state where clocks are supplied to the entire sub-system during the initialization operation. Accordingly, power consumption during the initialization operation (restoration period in Japanese Patent Application Laid-Open No. 2002-312073) is often greater than that during normal operations. Here, it is important to supply clocks in a state where a power supply voltage to the sub-system is stable during the initialization operation. However, if a clock is supplied in a state where the voltage is unstable as in Japanese Patent Application Laid-Open No. 2002-312073, power consumption increases.
In addition, time required for the power supply voltage to stabilize after the power supply starts varies depending on such factors as the scale (size, shape, position, number of pieces, number of gates, process types) of a power supply control target portion, to which the power supply is to start, and the conditions of other power supply control targets. However, with a method discussed in Japanese Patent Application Laid-Open No. 2002-312073, the reset time is set based on the operation clock frequency before a clock starts being supplied to the sub-system, and thus the reset time needs to be set long in consideration of the aforementioned factors, and it is hard to reduce power consumption.